Invention Grant
- Patent Title: Test pin configuration for test device for testing devices under test
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Application No.: US14970868Application Date: 2015-12-16
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Publication No.: US10197599B2Publication Date: 2019-02-05
- Inventor: Fu San Hiew , Siao Kiat Tan , Wee Kuan Tan , Arieff Ridzwan Yussuff , Murad Hudda , Wang Xiaojun , Ge Dandong , Yusman Sugianto , Tay Chyeo Yong , Lee Chow York , Gan Swee Lee
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R1/067
Abstract:
A test pin for a test device for electrically contacting a device under test to be tested, wherein the test pin comprises an electrically conductive base structure for electrically conducting a test signal between the device under test and the test device, and an exchangeable electrically conductive pin tip body configured to directly contact the device under test and to be exchangeably assembled with the base structure.
Public/Granted literature
- US20170176494A1 Test Pin Configuration for Test Device for Testing Devices Under Test Public/Granted day:2017-06-22
Information query
