Examples described herein emulate a processing architecture using multiple translations of the same source binary. A first translation binary includes compiler optimizations not present in a second translation binary. During runtime, a dispatcher directs control flow of a CPU when branch instructions are reached. Specifically, a dispatcher directs a CPU to execute instructions in the first translation binary, and accesses the second translation binary when an instruction is to a target that is not addressable in the first translation binary. The first and second translation binaries enable a target processing architecture to emulate a source processing architecture without just-in-time compilation or other runtime interpretation.