Invention Grant
- Patent Title: Semiconductor apparatus and design apparatus
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Application No.: US14964362Application Date: 2015-12-09
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Publication No.: US10198542B2Publication Date: 2019-02-05
- Inventor: Hiroyuki Iwata
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McGinn I.P. Law Group, PLLC.
- Priority: JP2015-054607 20150318
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G01R31/3185

Abstract:
In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.
Public/Granted literature
- US20160274184A1 SEMICONDUCTOR APPARATUS AND DESIGN APPARATUS Public/Granted day:2016-09-22
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