The gate driving circuit includes a shift register including a plurality of stages. An n-th stage among the plurality of stages includes: a pull-up switching element outputting a first clock to an output node in accordance with a voltage in a Q node, a pull-down switching element outputting a gate low voltage VGL to the output node in accordance with a voltage in a QB node, and a logic unit inverting and outputting a voltage in the Q node and a voltage in the QB node. The logic unit includes a first switching element including a gate to which a fourth clock is input and being between a start voltage line which supplies a start voltage and the Q node, a second switching element including a gate connected to the Q node and being connected to the QB node, a third switching element being between the second switching element and a gate low voltage line which supplies the gate low voltage, a fourth switching element including a gate to which a third clock is input and being between a gate high voltage line which supplies a gate high voltage and the QB node, a fifth switching element including a gate connected to the QB node and being between the Q node and the gate low voltage line, a first capacitor between the Q node and the output node, and a second capacitor between the gate low voltage line and the gate of the pull-down switching element.