Invention Grant
- Patent Title: Automatic delay-line calibration using a replica array
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Application No.: US14997901Application Date: 2016-01-18
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Publication No.: US10199082B2Publication Date: 2019-02-05
- Inventor: Steven Affleck , Jerome Beckmann
- Applicant: Avago Technologies International Sales Pte. Limited
- Applicant Address: SG Singapore
- Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
- Current Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
- Current Assignee Address: SG Singapore
- Agency: Sheridan Ross P.C.
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C7/06 ; G11C7/12 ; G11C17/18

Abstract:
A computer memory system, delay calibration circuit, and method of operating a delay calibration circuit are provided. The disclosed method includes providing a delay-line ring oscillator on silicon of a chip, providing at least one counter on the silicon of the chip, and measuring a chip-specific delay for performing an operation with the chip by synchronizing the at least one counter and operation of the delay-line ring oscillator with a timing trigger.
Public/Granted literature
- US20170206947A1 AUTOMATIC DELAY-LINE CALIBRATION USING A REPLICA ARRAY Public/Granted day:2017-07-20
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