Invention Grant
- Patent Title: Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
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Application No.: US15596812Application Date: 2017-05-16
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Publication No.: US10199087B2Publication Date: 2019-02-05
- Inventor: Michael C. Stephens, Jr.
- Applicant: III HOLDINGS 2, LLC
- Applicant Address: US DE Wilmington
- Assignee: III HOLDINGS 2, LLC
- Current Assignee: III HOLDINGS 2, LLC
- Current Assignee Address: US DE Wilmington
- Agency: Foley & Lardner LLP
- Main IPC: G11C11/4076
- IPC: G11C11/4076 ; G11C11/406 ; G11C5/06 ; G11C5/04 ; G11C29/02 ; G11C29/50 ; G11C5/14 ; G11C16/30 ; G11C5/02 ; G11C11/401 ; G11C7/10 ; G11C15/00 ; G11C11/4093 ; G11C11/4094 ; G11C29/44 ; G11C7/22

Abstract:
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
Public/Granted literature
Information query
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