Semiconductor and metal alloy interconnections for a 3D circuit
Abstract:
Fabrication of an integrated circuit comprising: at least one first transistor made at least partially in a first semiconducting layer, at least one second transistor made at least partially in a second semiconducting layer formed above the first semiconducting layer, an insulating layer formed between the first transistor and the second transistor, one or several connection elements passing through the insulating layer between the first and the second transistor, at least one connection element being connected to the first and/or the second transistor and being based on a metal-semiconductor alloy.
Public/Granted literature
Information query
Patent Agency Ranking
0/0