Alignment mark arrangement, semiconductor workpiece, and method for aligning a wafer
Abstract:
In various embodiments, an alignment mark arrangement may include a plurality of alignment marks disposed next to each other in a row, wherein at least one of the following holds true: a first alignment mark of the plurality of alignment marks has a first width and a second alignment mark of the plurality of alignment marks has a second width that is different from the first width; a first pair of neighboring alignment marks of the plurality of alignment marks is arranged at a first pitch and a second pair of neighboring alignment marks of the plurality of alignment marks is arranged at a second pitch that is different from the first pitch.
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