Invention Grant
- Patent Title: Alignment mark arrangement, semiconductor workpiece, and method for aligning a wafer
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Application No.: US14138161Application Date: 2013-12-23
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Publication No.: US10199330B2Publication Date: 2019-02-05
- Inventor: Andreas Woerz , Erwin Steinkirchner
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Viering, Jentschura & Partner mbB
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/66 ; G03F9/00

Abstract:
In various embodiments, an alignment mark arrangement may include a plurality of alignment marks disposed next to each other in a row, wherein at least one of the following holds true: a first alignment mark of the plurality of alignment marks has a first width and a second alignment mark of the plurality of alignment marks has a second width that is different from the first width; a first pair of neighboring alignment marks of the plurality of alignment marks is arranged at a first pitch and a second pair of neighboring alignment marks of the plurality of alignment marks is arranged at a second pitch that is different from the first pitch.
Public/Granted literature
- US20150179584A1 ALIGNMENT MARK ARRANGEMENT, SEMICONDUCTOR WORKPIECE, AND METHOD FOR ALIGNING A WAFER Public/Granted day:2015-06-25
Information query
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