Invention Grant
- Patent Title: Trench between stacked semiconductor substrates making contact with source-drain region
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Application No.: US15852519Application Date: 2017-12-22
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Publication No.: US10199409B2Publication Date: 2019-02-05
- Inventor: Francois Roy
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Crowe & Dunlevy
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L21/822 ; H01L21/768 ; H01L27/06 ; H01L27/11 ; H01L21/8234

Abstract:
A semiconductor device includes a first semiconductor substrate with a first transistor therein. The first transistor includes a first source-drain formed by a doped region in the first semiconductor substrate. An intermediary insulating layer is formed on and above the first semiconductor substrate. A second semiconductor substrate is formed on and above the intermediary insulating layer. A second transistor is formed in the second semiconductor substrate, and includes a second source-drain formed by a doped region in the second semiconductor substrate. A trench is formed in the second semiconductor substrate and in contact with the doped region for the second semiconductor substrate. The trench has a thickness equal to that of the second semiconductor substrate. Metal wiring extends from a contact with the doped region for the first source-drain, through the intermediary insulating layer and the trench, to make electrical contact with the doped region for the second source-drain.
Public/Granted literature
- US20180122846A1 TRENCH BETWEEN STACKED SEMICONDUCTOR SUBSTRATES MAKING CONTACT WITH SOURCE-DRAIN REGION Public/Granted day:2018-05-03
Information query
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