Synchronous N pulse burst generator
Abstract:
In accordance with an embodiment, a synchronous N pulse burst generator includes an input for an intermediate frequency trigger signal and a signal path extending from the input. The signal path includes a series of N AND gates and an OR gate. Each AND gate is arranged to receive two inputs from the signal path. The signal path introduces a time delay between the two inputs received by each AND gate. A second input of the two inputs is inverted. The signal path introduces the time delay between successive AND gates from the series of N AND gates. An OR gate receives outputs from the series of N AND gates and outputs an A/D clock signal.
Information query
Patent Agency Ranking
0/0