A method may include assigning a cacheability status to a page. The page may be in a memory of a host computer communicatively connected to a processor core on a field-programmable gate array (FPGA). The FPGA may include one or more caches. The method may further include obtaining an instruction including a reference to the page, determining, based on the cacheability status, whether the page is non-cacheable, and resolving the reference to the page, based on determining that the page is non-cacheable, bypassing the one or more caches of the FPGA.