Invention Grant
- Patent Title: System and method for reducing simulation time when simulating electrical circuits
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Application No.: US15166804Application Date: 2016-05-27
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Publication No.: US10204196B1Publication Date: 2019-02-12
- Inventor: Philippe Torregrossa , Arnaud Soury
- Applicant: Keysight Technologies, Inc.
- Applicant Address: US CA Santa Rosa
- Assignee: Keysight Technologies, Inc.
- Current Assignee: Keysight Technologies, Inc.
- Current Assignee Address: US CA Santa Rosa
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method are provided that reduce the amount of time required to perform transient circuit and envelope transient circuit simulations. The total simulation time is partitioned into n simulation segments of equal lengths of time and adjacent simulation segments are overlapped in time by a predetermined overlap time period, Tov. The simulation segments are then simulated in parallel and the simulation results are merged into a final simulation waveform. The predetermined overlap time period Tov is determined using a non-iterative process that can be performed very quickly. Consequently, the overall amount of time that is required to perform the simulation is greatly reduced.
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