Invention Grant
- Patent Title: Methods of forming features on integrated circuit products
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Application No.: US15797633Application Date: 2017-10-30
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Publication No.: US10204784B1Publication Date: 2019-02-12
- Inventor: Jinsheng Gao , Hui Zang , Haigou Huang
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L29/66 ; H01L21/308 ; H01L21/8238 ; H01L27/092

Abstract:
One illustrative method disclosed herein includes, among other things, forming an initial patterned etch mask above a feature-formation etch mask, the initial patterned etch mask including a plurality of laterally spaced-apart features having a non-uniform spacing, and performing at least one first etching process to remove an entire axial length of at least one of the plurality of features so as to thereby form a modified final patterned etch mask comprised of a plurality of features with a uniform spacing that defines a feature-formation pattern. In this example, the method also includes performing at least one second etching process so as to form a patterned feature-formation etch mask comprising the feature-formation pattern and performing at least one third etching process so as to form a plurality of features in a first layer, the features being formed with the feature-formation pattern.
Information query
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