Invention Grant
- Patent Title: Method for forming trench liner passivation
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Application No.: US15884304Application Date: 2018-01-30
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Publication No.: US10204822B2Publication Date: 2019-02-12
- Inventor: Cheng-Hsien Chou , Hung-Ling Shih , Tsun-Kai Tsao , Ming-Huei Shen , Kuo-Hwa Tzeng , Yeur-Luen Tu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/762

Abstract:
In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.
Public/Granted literature
- US20180174888A1 METHOD FOR FORMING TRENCH LINER PASSIVATION Public/Granted day:2018-06-21
Information query
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