In a method for manufacturing a semiconductor device, a cell well, a logic well and a high voltage well are formed in a first, a second and a third regions of a substrate. A first and a second stacked structures are formed on the first and second regions. A first and a second word line wells are formed in the cell well. First spacers are formed on sidewalls of the first and second stacked structures. A first gate oxide layer is formed on the third region and the first and second word line wells. A portion of the first stacked structure is removed to form a first and a second device structures. A second gate oxide layer is formed to cover the first, second and third regions. A first and a second word lines are formed adjacent to the first and second device structures.