Invention Grant
- Patent Title: Interface chip and built-in self-test method therefor
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Application No.: US14989035Application Date: 2016-01-06
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Publication No.: US10209302B2Publication Date: 2019-02-19
- Inventor: Yu-Lung Lin , Po-Chou Lin
- Applicant: VIA TECHNOLOGIES, INC.
- Applicant Address: TW New Taipei
- Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee Address: TW New Taipei
- Agency: McClure, Qualey & Rodack, LLP
- Priority: TW104112807A 20150422
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3187

Abstract:
An interface chip with a built-in self-test mechanism. An electrical physical layer (EPHY) provides a signal to a transmission terminal of the interface chip, and gets a signal from a reception terminal of the interface chip. A digital code generator generates a source code to be scrambled as a scrambled code and then encoded by an encoder and conveyed to the EPHY to be converted into the signal that is provided to the transmission terminal by the EPHY. The EPHY further converts the signal received from the reception terminal into a receiving code to be decoded by a decoder as a decoded code and then descrambled by the descrambler as a restored code. When the transmission terminal is coupled back to the interface chip via the reception terminal, the code checker checks whether the restored code matches the source code.
Public/Granted literature
- US20160313399A1 INTERFACE CHIP AND BUILT-IN SELF-TEST METHOD THEREFOR Public/Granted day:2016-10-27
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