According to one embodiment, a memory system is provided with a memory cell array, a first command issuing circuit and a controller. The memory cell array includes a plurality of data areas and a plurality of first parity areas. The data areas are arranged in a plurality of banks or in a plurality of chips, and individually store a plurality of data portions constituting access-unit data. The first parity areas are adjacent to the data areas and individually store a plurality of first parity portions constituting the first parity corresponding to the data. The first command issuing circuit issues a first command for the data areas and the first parity areas. The controller accesses the data areas and the first parity areas in response to the first command.