Invention Grant
- Patent Title: Optimizing quiescence in a software transactional memory (STM) system
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Application No.: US12344144Application Date: 2008-12-24
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Publication No.: US10210018B2Publication Date: 2019-02-19
- Inventor: Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon
- Applicant: Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F9/46
- IPC: G06F9/46

Abstract:
A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.
Public/Granted literature
- US20100162249A1 OPTIMIZING QUIESCENCE IN A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM Public/Granted day:2010-06-24
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