In certain aspects of the disclosure, an apparatus includes first and second semaphore registers disposed in a first power domain. A common address bus is coupled to the first and second semaphore registers, and a semaphore lock is disposed in the first power domain and coupled to the first and second semaphore registers. The semaphore lock is controlled by the first and second semaphore registers, and controls whether a signal from a second power domain is permitted to propagate to the first power domain. The first and second semaphore registers may be associated with first and second register addresses, respectively, which are selected to provide a substantially maximized Hamming distance between them. The first and second semaphore registers may have a write order expectation enforced between them.