Invention Grant
- Patent Title: Electrostatic damage protection circuitry verification
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Application No.: US14987737Application Date: 2016-01-04
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Publication No.: US10210302B2Publication Date: 2019-02-19
- Inventor: Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.
Public/Granted literature
- US20160117437A1 Electrostatic Damage Protection Circuitry Verification Public/Granted day:2016-04-28
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