An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2× data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2× functional blocks, and data spreading circuitry at the output of the 2× functional blocks.