A semiconductor memory device includes a memory cell transistor, a bit line, a sense amplifier circuit, a voltage generation circuit, and a control unit. The bit line is electrically connected to a terminal of the memory cell transistor. The sense amplifier circuit includes a first transistor having a gate electrically connected to the bit line and a second transistor connected in series to a first terminal of the first transistor. The control unit controls the voltage generation circuit to apply a first voltage to the second terminal of the first transistor during a first sense period and a second voltage to the second terminal of the first transistor during a second sense period. The first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V, and the first and second voltages have voltage levels different from each other.