A semiconductor memory device includes a plurality of memory cells, and a control circuit configured perform a multi-bit write operation on the memory cells in response to sequentially received commands including a first command and a second command, which is received after the first command, the first command including first bits to be written respectively in the memory cells and the second command including second bits to be written respectively in the memory cells. The multi-bit write operation includes at least a first write operation including at least one program operation that is initiated after receipt of the first command and prior to the receipt of the second command, and a second write operation that is initiated after receipt of the second command.