Invention Grant
- Patent Title: Semiconductor device
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Application No.: US15848133Application Date: 2017-12-20
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Publication No.: US10211286B2Publication Date: 2019-02-19
- Inventor: Toshiaki Sakata , Yasushi Niimura , Shunji Takenoiri
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: Rabin & Berdo, P.C.
- Priority: JP2015-076123 20150402; JP2015-217948 20151105
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/266

Abstract:
A first parallel pn layer having a first n-type region and a first p-type region junctioned alternately and repeatedly is disposed in an element active portion. The first parallel pn layer has a striped planar layout. A second parallel pn layer having a second n-type region and a second p-type region junctioned alternately and repeatedly is disposed in a high voltage structure. The second parallel pn layer has a striped planar layout in a direction identical to that of the first parallel pn layer. An intermediate region having a third parallel pn layer and a fourth parallel pn layer of a lower impurity quantity than the first parallel pn layer is disposed between the first and second parallel pn layers, and formed by diffusing impurity implanting regions becoming the first and the second parallel pn layers formed separated from each other to a region in which no impurity is ion-implanted.
Public/Granted literature
- US20180114832A1 SEMICONDUCTOR DEVICE Public/Granted day:2018-04-26
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