Invention Grant
- Patent Title: Charge trapping prevention III-Nitride transistor
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Application No.: US15184032Application Date: 2016-06-16
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Publication No.: US10211329B2Publication Date: 2019-02-19
- Inventor: Hyeongnam Kim , Mohamed Imam , Alain Charles , Jianwei Wan , Mihir Tungare , Chan Kyung Choi
- Applicant: Infineon Technologies Americas Corp.
- Applicant Address: US CA El Segundo
- Assignee: Infineon Technologies Americas Corp.
- Current Assignee: Infineon Technologies Americas Corp.
- Current Assignee Address: US CA El Segundo
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/20 ; H01L29/41 ; H01L29/205 ; H01L29/417 ; H01L29/423 ; H01L29/43 ; H01L29/06

Abstract:
There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.
Public/Granted literature
- US20170365701A1 Charge Trapping Prevention III-Nitride Transistor Public/Granted day:2017-12-21
Information query
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