Invention Grant
- Patent Title: Multiplier pipelining optimization with a postponed estimation correction
-
Application No.: US15696036Application Date: 2017-09-05
-
Publication No.: US10216483B2Publication Date: 2019-02-26
- Inventor: T. J. O'Dwyer , Pierre Laurent
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G06F7/523
- IPC: G06F7/523
Abstract:
One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
Public/Granted literature
- US20180107453A1 MULTIPLIER PIPELINING OPTIMIZATION WITH A POSTPONED ESTIMATION CORRECTION Public/Granted day:2018-04-19
Information query
