According to one embodiment, a memory system includes a nonvolatile first memory, a second memory which has a buffer, and a memory controller. The memory controller manages a plurality of pieces of translation information. In a case where the plurality of pieces of translation information include a first plurality of pieces of translation information, the memory controller caches first translation information among the first plurality of pieces of translation information and does not cache second translation information among the first plurality of pieces of translation information. The first plurality of pieces of translation information linearly correlates a plurality of continuous physical addresses with a plurality of continuous logical addresses.