Invention Grant
- Patent Title: Stacked semiconductor dies including inductors and associated methods
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Application No.: US15693039Application Date: 2017-08-31
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Publication No.: US10217726B1Publication Date: 2019-02-26
- Inventor: Eiichi Nakano
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L25/00

Abstract:
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprises a substrate, a first die mounted to the substrate and including first inductors, and a second die mounted to the first die in an offset position and including second inductors. The first inductors are at an active side of the first die, and the second inductors are at an active side of the second die. At least a portion of the first inductors are proximate and inductively coupled to the second inductors. The semiconductor device further comprises a first plurality of interconnects electrically coupling the substrate to the first die, and a second plurality of interconnects electrically coupling the second die to the substrate. The first plurality of interconnects extend from an upper surface of the substrate to the active side of the first die, and the second plurality of interconnects extend from the active side of the second die to the lower surface of the substrate.
Public/Granted literature
- US10177120B1 Stacked semiconductor dies including inductors and associated methods Public/Granted day:2019-01-08
Information query
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