Invention Grant
- Patent Title: High voltage integrated circuit with high voltage junction termination region
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Application No.: US15452035Application Date: 2017-03-07
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Publication No.: US10217861B2Publication Date: 2019-02-26
- Inventor: Masaharu Yamaji
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: Rabin & Berdo, P.C.
- Priority: JP2016-056061 20160318
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/40 ; H01L29/78

Abstract:
An nchMOSFET of a level-raising circuit is arranged in a high voltage junction termination region (HVJT), to be integrated with a parasitic diode formed by an n−-type diffusion region and a second p-type separation region. On a high potential side of the HVJT, a first field plate (FP) also acting as a drain electrode of the nchMOSFET and a second FP also acting as a cathode electrode of a parasitic diode are arranged away from each other. On a low potential side the HVJT, a third electrode also acting as a source electrode of the nchMOSFET is arranged in a planar layout surrounding the periphery of a high potential side region. On an interlayer insulating film, an interval between a first portion of the third FP and a fourth portion of the first FP is larger than an interval between the second and the third FPs.
Public/Granted literature
- US20170271506A1 SEMICONDUCTOR DEVICE Public/Granted day:2017-09-21
Information query
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