A circuit may include control circuitry configured to determine a duty cycle error for a sample clock signal. Based on the duty cycle error the control circuitry may determine a corrective direction by which to alter the duty cycle to correct the duty cycle error. The control circuitry may indicate the corrective direction to selection circuitry via a selection signal. Responsive to the selection signal, the selection circuitry may select a leading phase signal and a lagging phase signal from among a plurality of relative phase signals. Output circuitry may combine the leading phase signal and a lagging phase signal to generate an output clock signal with a duty cycle corresponding the corrective direction.