Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.