Invention Grant
- Patent Title: Method and system for efficient cache buffering supporting variable stripe sizes to enable hardware acceleration
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Application No.: US15335037Application Date: 2016-10-26
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Publication No.: US10223009B2Publication Date: 2019-03-05
- Inventor: Horia Simionescu , Timothy Hoglund , Sridhar Rao Veerla , Panthini Pandit , Gowrisankar Radhakrishnan
- Applicant: Avago Technologies International Sales Pte. Limited
- Applicant Address: SG Singapore
- Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
- Current Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
- Current Assignee Address: SG Singapore
- Agency: Sheridan Ross P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06 ; G06F12/0864 ; G06F12/0895 ; G06F12/0871 ; G06F12/0875

Abstract:
A system and method for efficient cache buffering are provided. The disclosed method includes receiving an Input/Output (I/O) command from a host system at a storage controller, parsing the I/O command at the storage controller with a host I/O manager to extract command instructions therefrom. The host I/O manager is able to generate at least one local message that includes the command instructions extracted from the I/O command and transmit the at least one local message to a cache manager. The cache manager is enabled to work in local memory to execute the command instructions contained in the at least one message. The cache manager is also configured to chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system.
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