A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.