A data holding device 100 has an inverter loop 101, a differential pair circuit 102 connected to the ground terminals of inverters, a first potential setter 103 configured to turn the output terminals of the inverters to a first potential (VDD), and a second potential setter 104 configured to turn the ground terminals of the inverters to a second potential (VSS). During data holding, the differential pair circuit 102 and the first potential setter 103 are disabled so that the ground terminals of the inverters are at the second potential. During data writing, the differential pair circuit 102 is disabled so that the output terminal of one inverter is at the first potential and the ground terminal of the other inverter is at the second potential.