Invention Grant
- Patent Title: Three dimensional NAND memory device with common bit line for multiple NAND strings in each memory block
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Application No.: US15078555Application Date: 2016-03-23
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Publication No.: US10224104B2Publication Date: 2019-03-05
- Inventor: Murshed Chowdhury , Jin Liu , Yanli Zhang , Andrew Lin , Raghuveer S. Makala , Johann Alsmeier
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: The Marbury Law Group PLLC
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/26 ; G11C16/04 ; H01L27/11582 ; H01L27/11524 ; H01L27/11556 ; H01L27/1157

Abstract:
Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.
Public/Granted literature
- US20170278571A1 THREE DIMENSIONAL NAND MEMORY DEVICE WITH COMMON BIT LINE FOR MULTIPLE NAND STRINGS IN EACH MEMORY BLOCK Public/Granted day:2017-09-28
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