Invention Grant
- Patent Title: Low temperature thin wafer backside vacuum process with backgrinding tape
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Application No.: US15187729Application Date: 2016-06-20
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Publication No.: US10224223B2Publication Date: 2019-03-05
- Inventor: Eric J. Li
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/68
- IPC: H01L21/68 ; H01L21/67 ; H01L21/683 ; H01L21/768 ; B32B43/00

Abstract:
Vacuum processing, such as a backside metallization (BSM) deposition, is performed on a taped wafer after a gas escape path is formed between a base film of the tape and the wafer frontside surface following backgrind. Venting provided by the gas escape path reduces formation of bubbles under the tape. The gas escape path may be provided, for example, by a selective pre-curing of tape adhesive, to breach an edge seal and place the wafer frontside surface internal to the edge seal in fluid communication with an environment external to the edge seal. With the thinned wafer supported by the pre-cured tape, BSM is then deposited while the wafer and tape are cooled, for example, via a cooled electrostatic chuck.
Public/Granted literature
- US20160300743A1 LOW TEMPERATURE THIN WAFER BACKSIDE VACUUM PROCESS WITH BACKGRINDING TAPE Public/Granted day:2016-10-13
Information query
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