Invention Grant
- Patent Title: Merged gate for vertical transistors
-
Application No.: US15474564Application Date: 2017-03-30
-
Publication No.: US10224249B2Publication Date: 2019-03-05
- Inventor: Brent A. Anderson , Fee Li Lie , Edward J. Nowak , Junli Wang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/32 ; H01L21/82 ; H01L27/08 ; H01L29/06 ; H01L27/092 ; H01L21/28 ; H01L29/423 ; H01L21/8238 ; H01L21/3213 ; H01L21/8234 ; H01L27/088
Abstract:
Embodiments of the invention are directed to a semiconductor structure that includes a first fin structure having a first sidewall, a first gate structure adjacent a lower portion of the first sidewall, and a first spacer structure over the first gate structure and adjacent an upper portion of first the sidewall. The first spacer structure includes a first spacer structure thickness dimension that extends in a first direction away from the first sidewall. The first gate structure includes a first gate structure thickness dimension that extends in the first direction away from the first sidewall. The first gate structure dimension is about equal to the first spacer structure thickness dimension.
Public/Granted literature
- US20180005902A1 MERGED GATE FOR VERTICAL TRANSISTORS Public/Granted day:2018-01-04
Information query
IPC分类:
