- Patent Title: Through-substrate via power gating and delivery bipolar transistor
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Application No.: US15805210Application Date: 2017-11-07
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Publication No.: US10224410B2Publication Date: 2019-03-05
- Inventor: Gerald K. Bartley , David P. Paulsen , John E. Sheets, II
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/73 ; H01L29/08 ; H01L23/00 ; H01L29/732

Abstract:
Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through-substrate via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through-substrate via can also include metal contacts to the collector, base, and emitter which enable the through-substrate via to be coupled to a metal routing layer or a solder bump.
Public/Granted literature
- US20180350942A1 THROUGH-SUBSTRATE VIA POWER GATING AND DELIVERY BIPOLAR TRANSISTOR Public/Granted day:2018-12-06
Information query
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