Invention Grant
- Patent Title: Precise junction placement in vertical semiconductor devices using etch stop layers
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Application No.: US15652924Application Date: 2017-07-18
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Publication No.: US10224429B2Publication Date: 2019-03-05
- Inventor: Huiming Bu , Liying Jiang , Siyuranga O. Koswatta , Junli Wang
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/08 ; H01L21/306 ; H01L21/02 ; H01L29/20 ; H01L29/739 ; H01L29/165 ; H01L29/205
Abstract:
A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.
Public/Granted literature
- US20170365714A1 PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS Public/Granted day:2017-12-21
Information query
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