Invention Grant
- Patent Title: Dual signal protocol input/output (I/O) buffer circuit
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Application No.: US15086887Application Date: 2016-03-31
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Publication No.: US10224911B1Publication Date: 2019-03-05
- Inventor: Tat Hin Tan , Choong Kit Wong , Ker Yon Lau , Hsiao Wei Su , Hoong Chin Ng
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H03K5/007
- IPC: H03K5/007

Abstract:
An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.
Information query
IPC分类: