Invention Grant
- Patent Title: Multi-layer semiconductor structure and methods for fabricating multi-layer semiconductor structures
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Application No.: US15271755Application Date: 2016-09-21
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Publication No.: US10229897B2Publication Date: 2019-03-12
- Inventor: Rabindra N. Das
- Applicant: Massachusetts Institute of Technology
- Applicant Address: US MA Cambridge
- Assignee: Massachusetts Institute of Technology
- Current Assignee: Massachusetts Institute of Technology
- Current Assignee Address: US MA Cambridge
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L23/48 ; H01L23/522 ; H01L23/532 ; H01L25/065 ; H01L25/00 ; H01L21/48 ; H01L23/538 ; H01L23/498 ; H01L23/00 ; H01L21/18 ; H01L21/306 ; H01L21/768 ; H01L23/528

Abstract:
A multi-layer semiconductor device (or structure) includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces. Additionally, each of the at least two semiconductor structures includes a first section having first and second opposing surfaces and a plurality of electrical connections extending between select portions of the first and second surfaces. Each of the at least two semiconductor structures also includes a second section having first and second opposing surfaces, with the first surface of the second section disposed over and coupled to the second surface of the first section. Methods for fabricating a multi-layer semiconductor structure from a plurality of semiconductor structures are also provided.
Public/Granted literature
- US20170194248A1 Multi-Layer Semiconductor Structure and Methods for Fabricating Multi-Layer Semiconductor Structures Public/Granted day:2017-07-06
Information query
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