Invention Grant
- Patent Title: Separate N and P fin etching for reduced CMOS device leakage
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Application No.: US15593872Application Date: 2017-05-12
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Publication No.: US10229910B2Publication Date: 2019-03-12
- Inventor: Isabel C. Chu , Lawrence A. Clevenger , Leigh Anne H. Clevenger , Mona A. Ebrish , Gauri Karve , Fee Li Lie , Deepika Priyadarshini , Nicole A. Saulnier , Indira P. Seshadri
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L27/092 ; H01L21/8238 ; H01L21/308 ; H01L21/3105 ; H01L29/10 ; H01L29/161 ; H01L29/167 ; H01L21/02
Abstract:
A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.
Public/Granted literature
- US20180097002A1 SEPARATE N AND P FIN ETCHING FOR REDUCED CMOS DEVICE LEAKAGE Public/Granted day:2018-04-05
Information query
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