Invention Grant
- Patent Title: Methods of forming memory devices with isolation structures
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Application No.: US15153036Application Date: 2016-05-12
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Publication No.: US10229922B2Publication Date: 2019-03-12
- Inventor: Badih El-Kareh , Leonard Forbes
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L27/11524 ; H01L21/28 ; H01L27/115 ; H01L27/11521 ; H01L29/66 ; H01L29/788 ; G11C16/04 ; G11C16/10 ; H01L29/06
Abstract:
A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.
Public/Granted literature
- US20160254270A1 METHODS OF FORMING MEMORY DEVICES WITH ISOLATION STRUCTURES Public/Granted day:2016-09-01
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