Invention Grant
- Patent Title: Semiconductor device and manufacturing method of semiconductor device
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Application No.: US15904701Application Date: 2018-02-26
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Publication No.: US10229992B2Publication Date: 2019-03-12
- Inventor: Yoshinao Miura , Hironobu Miyamoto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Koutou-ku, Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Koutou-ku, Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2017-084350 20170421
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/20 ; H01L29/205 ; H01L29/06 ; H01L29/417 ; H01L29/47 ; H01L21/02 ; H01L29/66 ; H01L21/3213 ; H01L21/306 ; H01L21/027 ; H01L21/285

Abstract:
Characteristics of a semiconductor device are improved.A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.
Public/Granted literature
- US20180308968A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Public/Granted day:2018-10-25
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