A phase locked loop comprises: a controllable oscillator 102; a variable divider arrangement 108, 110 which takes a signal from the controllable oscillator 102 and divides it by a variable amount to provide a lower frequency signal; a sigma-delta modulator 112 arranged to provide a control input to said variable divider arrangement 108, 110; and a phase detector triggered 104 by said lower frequency signal and a reference clock; wherein said phase locked loop is arranged to be operable in a normal mode in which the controllable oscillator 102 is controlled by a voltage from said phase detector 104 and a calibration mode in which the controllable oscillator 102 is controlled digitally by a signal from a calibration module 114 which receives an input from said variable divider arrangement 108, 110.