- Patent Title: Efficient management of paged translation maps in memory and flash
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Application No.: US15197196Application Date: 2016-06-29
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Publication No.: US10235287B2Publication Date: 2019-03-19
- Inventor: Ajith Kumar Battaje , Tanay Goel , Rajendra Prasad Mishra
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Gabriel Fitch
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/1009

Abstract:
A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request to select translation table entries to store in a storage device, determine a plurality of translation table entries associated with a dump unit, allocate the plurality of translation table entries into a first group of translation table entries associated with a first node and a second group of translation table entries associated with a second node, the first group of translation table entries being frequently accessed and the second group of translation table entries being rarely accessed. determine a first status associated with a first recent access bit for a first translation table entry, the first translation table entry being included in the first group of translation table entries, and add the first translation table entry to the second group of translation table entries.
Public/Granted literature
- US20180004656A1 Efficient Management of Paged Translation Maps In Memory and Flash Public/Granted day:2018-01-04
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