Invention Grant
- Patent Title: Method of manufacturing a semiconductor device with epitaxial layers and an alignment mark
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Application No.: US15379533Application Date: 2016-12-15
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Publication No.: US10236258B2Publication Date: 2019-03-19
- Inventor: Andreas Moser , Hans Weber , Michael Treu , Johannes Baumgartl , Gabor Mezoesi
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Priority: DE102015122828 20151223
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L23/544 ; H01L21/266 ; H01L21/308 ; G03F9/00
Abstract:
An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 μm and a vertical extension in a range 100 nm to 1 μm. The alignment mark further includes at least one fin within the groove at a distance of at least 60 μm to a closest one of inner corners of the groove.
Public/Granted literature
- US20170186695A1 Method of Manufacturing a Semiconductor Device with Epitaxial Layers and an Alignment Mark Public/Granted day:2017-06-29
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