Invention Grant
- Patent Title: Semiconductor integrated circuit apparatus and manufacturing method for same
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Application No.: US15595306Application Date: 2017-05-15
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Publication No.: US10236286B2Publication Date: 2019-03-19
- Inventor: Katsuyoshi Matsuura , Junichi Ariyoshi
- Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
- Applicant Address: JP Kuwana-shi
- Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
- Current Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
- Current Assignee Address: JP Kuwana-shi
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2014-003914 20140114
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L21/8234 ; H01L21/8238 ; H01L27/07 ; H01L27/06 ; H01L27/11517 ; H01L21/265 ; H01L29/66 ; H01L29/78

Abstract:
A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
Public/Granted literature
- US20170250177A1 SEMICONDUCTOR INTERGRATED CURCUIT APPARATUS AND MANUFACTURING METHOD FOR SAME Public/Granted day:2017-08-31
Information query
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