Invention Grant
- Patent Title: Three dimensional monolithic LDMOS transistor
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Application No.: US15782473Application Date: 2017-10-12
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Publication No.: US10236354B2Publication Date: 2019-03-19
- Inventor: Qing Liu , Shom Ponoth
- Applicant: Avago Technologies International Sales Pte. Limited
- Applicant Address: SG Singapore
- Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
- Current Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
- Current Assignee Address: SG Singapore
- Agency: Foley & Lardner LLP
- Main IPC: H01L27/13
- IPC: H01L27/13 ; H01L29/417 ; H01L49/02 ; H01L27/06 ; H01L27/12 ; H01L29/786 ; H01L21/768 ; H01L23/485

Abstract:
A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source I drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.
Public/Granted literature
- US20180033860A1 THREE DIMENSIONAL MONOLITHIC LDMOS TRANSISTOR Public/Granted day:2018-02-01
Information query
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