The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.